With increasing requirements of information technologies and users on services such as multimedia, demands of communication systems on large capacity and free scheduling ability become increasingly high as well.
A good solution for free scheduling requirements of communication systems is the large capacity switch technology, which implements free service scheduling. However, during the free service scheduling, a situation may occur where in the same system device, data signals and their corresponding clock and enable signals are input, and after processed and scheduled by the system, the output data signals cannot use the same clock as the input data signals as the sending clock.
When the input clock of the system device is equal to the output clock, they are generally local data input and local data output, such as ingress A input of No. 1 board, and egress B output of No. 1 board. Such local data scheduling cannot fully meet the free scheduling requirements of the communication systems.
During remote free service scheduling, for example, data is input from ingress A of Beijing No. 1 board and output from egress B of Guangzhou No. 2 board, and a sending clock is required to be generated locally.
Currently, the sending clock is generated at a fixed ratio or by externally connecting a phase lock loop.
In the current method for generating the sending clock, when a sending frequency of service data changes, the generated sending clock no longer matches the data. When the sending frequency of the data changes significantly, that is, when jitter of the corresponding sending clock is relatively large but still within an allowable range of jitter, clock is generated at a fixed ratio such that the data is no longer sent effective and drift of the data is serious, and at the same time, because of mismatch between the sending clock and the sent data, the bit error rate of the sent data of the adapter is increased and frequency locking is difficult. When the sending frequency of the data changes significantly and the jitter of the sending clock has exceeded the allowable range of jitter, the system will not be able to send data at this point.